Sample and Hold With Offset Adjustment

This is a simple sample and hold with offset adjustment circuit. Sample and hold circuit is used to operate on analog information in a time frame which is expedient. This circuit works by sampling a segment of the information and holding it. And then convert it into some readout or form of control signal. Here is the circuit:

This circuit uses the 2N4339 JFET because it has low pinch-off voltage, very-low ID(off) (<50pA), and low IGSS(<100pA). This is a low leakage circuit, because the leakage level of this circuit is on clean, solder-resin free. [Source: National Semiconductor Application Note]